CMP is a single-side polishing process that is usually used for reducing the roughness of the front side of a semiconductor wafer. It is therefore also referred to as mirror polishing. During the CMP, the semiconductor wafer is pressed with the side to be polished against a rotating polishing pad by a rotating polishing head and is smoothed in the presence of a polishing agent supplied. The material removal brought about during polishing depends, inter alia, on the pressure with which the semiconductor wafer is pressed against the polishing pad. There is also the possibility of choosing the polishing pressure to be different in different zones, thus bringing about a material removal which leads to a non-uniform profile if the material removal is considered along the diameter of the semiconductor wafer. Pressure zones can be established with the aid of pressure chambers or pressure rings, for example. A polishing head having a carrier which enables subdivision into pressure zones is described in U.S. Pat. No. 5,916,016, for example. CMP can accordingly also be used for influencing the geometry of the semiconductor wafer in a targeted manner, that is to say the parameters of the semiconductor wafer which describe the local and global flatness. CMP methods are disclosed for example in US 2002-0077039 and also in US 2008-0305722.
In addition to CMP, DSP (double-side polishing) plays an important part in the polishing of semiconductor wafers. During DSP, generally a plurality of semiconductor wafers are polished simultaneously. During DSP, a semiconductor wafer lies between two polishing plates provided with a polishing pad in a cutout in a carrier disk and is polished on both sides with the aid of a polishing agent supplied. DSP has the task, in particular, of eliminating instances of damage in the region of the surface that have remained after shaping mechanical processing by lapping? and/or grinding of the semiconductor wafer. The material removal during DSP, with a total removal of usually 10 to 30 μm, is significantly greater than that in the case of CMP. Therefore, DSP is often also referred to as stock removal polishing.
In addition, so-called “fixed abrasive polishing” (FAP) technologies are already known, in which the semiconductor wafer is polished on a polishing pad containing an abrasive material bonded in the polishing pad (“fixed-abrasive pad”). A polishing step in which such an FAP polishing pad is used is referred to hereinafter for short as the FAP step.
German patent application DE 102 007 035 266 A1 describes a method for polishing a substrate composed of silicon material, comprising two polishing steps of the FAP type, which differ in that, during one polishing step, a polishing agent slurry containing unbonded abrasive material as solid material is introduced between the substrate and the polishing pad, while during the second polishing step the polishing agent slurry is replaced by a polishing agent solution which is free of solids.
The thickness of a semiconductor wafer polished by means of DSP usually decreases significantly toward the edge. This edge roll-off can adversely affect the global flatness and the local flatness in edge areas. It is desirable, therefore, to limit the edge roll-off as far as possible to the region of the edge exclusion.
During the single-side polishing of a group of a plurality of semiconductor wafers (“single-side batch polishing”), the semiconductor wafers are mounted by one side onto the front side of a carrier plate by virtue of a positively locking and force-locking connection, for example by adhesion, adhesive bonding, cementing or vacuum application, being produced between the side and the carrier plate.
A method for producing an adhesive-bonding connection between a carrier plate and a semiconductor wafer is described in DE 198 16 150 A1.
All known types of adhesive-bonding connections and fixing means shall be noted hereinafter under the expressions “cementing” and “cementing on” and also “cement”.
In general, the semiconductor wafers are mounted onto the carrier plate in such a way that they form a concentric ring or a pattern of concentric rings. However, there are also polishing methods in which only one respective semiconductor wafer is mounted onto a carrier plate. The rear side of the carrier plate is supported by a pressure plunger, called polishing head hereinafter. After mounting, the free wafer sides are pressed with a specific polishing force against a polishing plate, over which a polishing pad is stretched, and polished with a polishing agent being supplied. In this case, the carrier plate and the polishing plate are usually rotated at different speeds. The necessary polishing force is transmitted from the polishing head to the rear side of the carrier plate. A large number of the polishing machines used are designed such that they have a plurality of polishing heads and can accordingly accommodate a plurality of carrier plates. Polishing machines of this type are described in the document U.S. Pat. No. 5,908,347, for example.
In the course of this single-side polishing (SSP) in the batch method, a typical local geometry fault occurs, the so-called “roll-off”. This is an edge roll-off at the front side of the semiconductor wafer at the location which faces outward relative to the carrier plate, that is to say which is at the smallest distance from the edge of the carrier plate. In the case where only one respective semiconductor wafer is mounted onto a carrier plate, an edge roll-off can likewise occur, which, however, is not restricted to one location of the semiconductor wafer but rather occurs over the entire circumference of the wafer.
According to the prior art, this geometry fault is minimized by suitable conditioning of the polishing pad in the radially outer region. Such pad conditioning is described in JP 11-226860 A, for example. This method does not enable the edge roll-off to be completely eliminated, however.
US2003/0022495 A1 proposes, for the purpose of reducing the edge roll-off, firstly polishing the rear side of the semiconductor wafer in such a way that a reference plane arises. For this purpose, the front side is sucked (“chucked”) onto a stiff carrier and a material removal is brought about on the rear side, said material removal preferably amounting to 3 to 8 μm. Afterward, the front side of the semiconductor wafer is polished.
The German application having the file reference 102008045534.2, not previously published, discloses methods for polishing a semiconductor wafer, comprising polishing the rear side of the semiconductor wafer by means of CMP, wherein a material removal with a profile along the diameter of the semiconductor wafer is produced according to which the material removal is greater in a center region of the rear side than in an edge region of the rear side; and polishing the front side of the semiconductor wafer by means of CMP, wherein a material removal with a profile along the diameter of the semiconductor wafer is produced according to which the material removal is smaller in a center region of the front side than in an edge region of the front side.
What is disadvantageous about this method is that during the CMP polishing of the front side, the rear side of the semiconductor wafer is CMP-polished and therefore it has a very smooth surface, which, upon the semiconductor wafer being fixed by its rear side on a carrier, leads to problems in respect of preventing the semiconductor wafer from floating away therefrom during polishing.